The technology incorporates process-qualified MTP IP blocks jointly developed with Virage Logic. The new technology is the first 2.5 volt MTP process, breaking the heretofore 3.3 volt baseline barrier. It eliminates the need for an external EEPROM currently in many systems applications, thereby reducing power, area and costs while increasing data security.
Built on TSMC's 65nm Low Power (LP) process, the new MTP technology features up to 8k bits memory size that is ideal for small memory requirements associated with MP3 music downloadable digital rights management, RFID devices, fingerprint identification applications, and pre-paid cash or phone cards.
The 65nm MTP process is built up to 10 metal layers using copper low-k interconnects and nickel silicide transistor interconnects. The technology is fully logic-compatible and the NVM memory requires no additional processes or masks. Devices built using the process will support full read and program operations across temperatures ranging from -40 degrees C to 125 degrees C, with minimum 10-year data retention at 125 degrees C.
